The present invention relates to a timing generator which is capable of generating arbitrarily delayed pulses which can be used in an IC tester, for example.
The IC tester comprises, as shown in FIG. 1, a timing generator 11, a pattern generator 12 which generates test pattern signals in response to timing signals P.sub.1, P.sub.2, P.sub.3, . . . from the timing generator 11, a formatter 13 which converts the test pattern signals from the test pattern generator 12 into a real waveform for input into a device under test (hereinafter referred to simply as DUT) 14, a data latch circuit 15 which latches a response output signal from the DUT 14, and a logic comparator 16 which compares the response output signal latched in the data latch circuit 15 and an expected value pattern from the pattern generator 12 to determine whether the DUT 14 is good or not.
In the timing generator 11 there are present period data A.sub.1, A.sub.2, A.sub.3, . . . for defining the time intervals at which the test pattern signals are generated and delay data K.sub.1, K.sub.2, K.sub.3, . . . which correspond to the period data A.sub.1, A.sub.2, A.sub.3, . . , respectively. When supplied with a start pulse Ps from the outside, the timing generator 11 outputs the timing signals P.sub.1 k , P.sub.2, P.sub.3, . . . at the time intervals defined by the period data A.sub.1, A.sub.2, A.sub.3, . . . , and the pattern generator 12 yields the test pattern signals in response to the timing signals P.sub.1, P.sub.2, P.sub.3, . . .
The delay data K.sub.1, K.sub.2, K.sub.3, . . . are timed to the generation of response output signals which are provided from the DUT 14 supplied with test patterns in accordance with the timing signals P.sub.1, P.sub.2, P.sub.3, . . . At the timing set by the timing generator 11 in dependence on the delay data K.sub.1, K.sub.2, K.sub.3, . . strobe pulses S.sub.1, S.sub.2, S.sub.3, . . . are generated and applied to the latch circuit 15.
The timing for generating the strobe pulses S.sub.1, S.sub.2, S.sub.3, . . . is usually set so that they are delayed behind the generation of the timing pulses P.sub.1, P.sub.2, P.sub.3, . . . for periods K.sub.1, K.sub.2, K.sub.3, . . . , respectively, which are shorter than the corresponding periods of the time intervals A.sub.1, A.sub.2, A.sub.3, . . . at which the test patterns are produced, as shown in FIGS. 2A and 2B. However, there are times, for example, as depicted in FIGS. 3A and 3B, when the strobe pulse S.sub.1 is to be generated in the next period as a result of setting the period data A.sub.1 to a shorter period of time. In such an instance, it is customary in the prior art to employ a method in which a flag "NEXT" is set for the delay data K.sub.1, a calculation K.sub.1 -A.sub.1 =M.sub.1 is performed to obtain delay data, and the strobe pulse S.sub.1 is generated the time M.sub.1 behind the beginning of the next period.
According to the prior art in the case of generating each of the strobe pulses S.sub.1, S.sub.2, S.sub.3, . . . at the timing beyond the limits of the corresponding period, the flag "NEXT" is set and the delay time M.sub.1 is defined relative to the beginning of the next period, and consequently, the allowable delay time is limited only to the range of the next period. It is therefore impossible, with the prior art, to test a device which outputs a response signal after as much delay is several cycles of the timing pulse, such as a central processor.